In the fabrication of silicon integrated circuits, the continuing increase in the number of devices on a chip and the accompanying decrease in the minimum feature sizes have placed increasingly difficult demands upon many of the many fabrication steps used in their fabrication including depositing layers of different materials onto sometimes difficult topologies and etching further features within those layers.
Oxide etching has presented some of the most difficult challenges. Oxide is a somewhat generic term used for silica, particularly silicon dioxide (SiO.sub.2) although slightly non-stoichiometric compositions SiO.sub.x are also included, as is well known. The term oxide also covers closely related materials, such as oxide glasses including borophosphosilicate (BPSG). Some forms of silicon oxynitride are considered to more closely resemble a nitride than an oxide. Oxide materials are principally used for electrically insulating layers, often between different levels of the integrated circuit. Because of the limits set by dielectric breakdown, the thickness of the oxide layers cannot be reduced to much below 0.5 to 1 .mu.m. However, the minimum feature size of contact and via holes penetrating the oxide layer is being pushed to well below 0.5 .mu.m. The result is that the holes etched in the oxide must be highly anisotropic and must have a high aspect ratio of the depth to the minimum width of the hole. A further problem arises from the fact that the underlying silicon may be formed with active doped regions of thicknesses substantially less than the depth of the etched hole (the oxide thickness). Due to manufacturing variables, it has become impossible to precisely time a non-selective oxide etch to completely etch through the silicon oxide without a substantial probability of also etching through the underlying active silicon region.
The anisotropy can be achieved in dry plasma etching in which an etching gas, usually a halocarbon, is electrically excited into a plasma. The plasma conditions may be adjusted to produce highly anisotropic etching in many materials. However, the anisotropy should not be achieved by operating the plasma reactor in a pure sputtering mode in which the plasma ejects particles toward the wafer with sufficiently high energy that they sputter the oxide. Sputtering is generally non-selective, and high-energy sputtering also seriously degrades semiconducting silicon exposed at the bottom of the etched contact hole.
In view of these and other problems, selective etching processes have been developed which depend more upon chemical effects. A sufficiently high degree of selectivity allows new structures to be fabricated without the need for precise lithography for each level.
An example of such an advanced structure is a self-aligned contact (SAC), illustrated in the cross-sectional view of FIG. 1. A SAC structure for two transistors is formed on a silicon substrate 10. A polysilicon gate layer 12, a tungsten silicide barrier and glue layer 14, and a silicon nitride cap layer 16 are deposited and photolithographically formed into two closely spaced gate structures 18 having a gap 20 therebetween. Chemical vapor deposition is then used to deposit onto the wafer a substantially conformal layer 22 of silicon nitride (Si.sub.3 N.sub.4), which coats the top and sides of the gate structures 18 as well as the bottom 23 of the gap 20. The nitride acts as an electrical insulator. Dopant ions are ion implanted using the gate structures 18 as a mask to form a self-aligned p-type or n-type well 24, which acts as a common source for the two transistors having respective gates 18. The drain structures of the transistors are not illustrated.
An oxide field layer 24 is deposited over this previously defined structure, and a photoresist layer 26 is deposited over the oxide layer 24 and photographically defined into a mask so that a subsequent oxide etching step etches a contact hole 28 through the oxide layer 24 and stops on the underlying nitride layer 22. It is called a contact hole because the metal subsequently deposited into the contact hole 28 contacts silicon rather than a metal layer. A post-etch sputter removes the portion of the nitride layer 22 at the bottom 23 of the gap 20. The silicon nitride acts as an electrical insulator for the metal, usually aluminum, thereafter filled into the contact hole 28.
Because the nitride acts as an insulator, the SAC structure and process offer the advantage that the contact hole 28 may be wider than the width of the gap 20 between the gate structures 18. Additionally, the photographic registry of the gate structures 18 with the contact hole 28 need not be precise. However, to achieve these beneficial effects, the SAC oxide etch must be highly selective to nitride. That is, the process much produce an oxide etch rate that is must greater than the nitride etch rate. Numerical values of selectivity are calculated on the ratio of the oxide to nitride etch rates. Selectivity is especially critical at the corners 29 of the nitride layer 22 above and next to the gap 20 since the corners 29 are the portion of the nitride exposed the longest to the oxide etch and have a geometry favorable to fast etching.
Furthermore, increased selectivity is being required with the increased usage of chemical mechanical polishing (CMP) for planarization. CMP is sensitive to wafer waviness with the effect that a flat oxide surface over a wavy substrate results in an oxide of significantly varying thickness. As a result, the time of the oxide etch must be set significantly higher, say by 100%, than the etch of the design thickness to assure penetration of the oxide. This is called over etch, which also accounts for other variations. However, for the regions with a thinner oxide, the nitride is exposed that much longer to the etching environment.
Ultimately, the required degree of selectivity is reflected in the probability of an electrical short between the gate structures 18 and the metal filled into the contact hole 28. However, scanning electron micrographs (SEMs) of the etched structure of FIG. 1 quickly reveal if an excessive amount of nitride is being removed. The etch must also be selective to photoresist, for example at facets that develop at the mask corners, but the requirement of photoresist selectivity is not so stringent since the photoresist layer 26 may be made much thicker than the nitride layer 22.
Blalock et al. have disclosed a SAC oxide etch process in U.S. Pat. No. 5,286,344. Their sole detailed example using an etching gas of relative composition is given in TABLE 1, as near as can be understood. Note, however, that the percentages sum to greater than 100%.
TABLE 1 ______________________________________ Relative Gas Amount ______________________________________ CF.sub.4 16% CHF.sub.3 9% CH.sub.2 F.sub.2 20% Ar 57% ______________________________________
They use a plasma reactor having two opposed capacitor plates. The lower capacitor plate supports the wafer, and 500 W of RF power is applied to the lower plate. The upper plate and the rest of the chamber are grounded. Static or low-frequency induction coils are placed to the side of the chamber to apply 500 gauss of nearly static magnetic field to the plasma. That is, the process is magnetically enhanced reactive ion etching. The etching gas is maintained at a chamber pressure of 200 milliTorr. Blalock et al. achieve a nitride selectivity of 30:1 and an etch rate of 400 nm/min. The selectivity is satisfactory, but the etch rate is considered to be low. Adopting the recipe of Blalock et al. to an advanced etcher utilizing a high-density plasma is problematic.
In the future, the most demanding etching steps are projected to be performed with high-density plasma (HDP) etch reactors. Such HDP etch reactors achieve a high-density plasma having an ion density of 10.sup.11 cm.sup.-3 and above across the plasma exclusive of the sheathes. Although several techniques are available for achieving a high-density plasma are available such as electron cyclotron resonance and remote plasma sources, the commercially most important technique involves inductively coupling RF energy into the source region. The inductive coil may be cylindrically wrapped around the sides of chamber or be a flat coil above the top of the chamber or represent some intermediate geometry. An example of such an inductively coupled etch reactor is illustrated in the cross-sectional view of FIG. 2 and represents the IPS Etch Reactor available from Applied Materials, Inc. of Santa Clara, Calif. and described by Collins et al. in U.S. patent application Ser. No. 08/733,544, filed Oct. 21, 1996. As shown in FIG. 2, a wafer 30 to be processed is tightly supported on a cathode pedestal 32 supplied with RF power from a first RF power supply 34. The RF power applied to the pedestal 32 creates a DC self-bias field at the edge of the plasma next to the wafer 30. A silicon ring 36 surrounds the pedestal 32 and is controllably heated by an array of heater lamps 38. A grounded silicon wall 40 surrounds the plasma processing area. A silicon roof 42 overlies the plasma processing area, and lamps 44 and water cooling channels 46 control its temperature. The temperature-controlled silicon ring 36 and silicon roof 42 scavenge fluorine from the fluorocarbon plasma. Processing gases are supplied from a plurality of gas sources 47 and are controlled by respective mass flow controllers 48 before being combined and injected into the chamber through a top gas feed 50 formed in the roof 42. The top gas feed 50 has a showerhead dispensing structure including a distribution cavity and fifteen 250 .mu.m holes through the silicon roof 42 connecting the cavity to the chamber. An unillustrated vacuum pumping system connected to a pumping channel 52 around the lower portion of the chamber maintains the chamber at a preselected pressure.
In the used configuration, the silicon roof 42 is grounded, but its semiconductor resistivity and thickness are chosen to pass generally axial RF magnetic fields produced by an inner inductive coil stack 56 and an outer inductive coil stack 58 powered by respective RF power supplies 60, 62. However, a single RF power supply with an adjustable power splitter may be used. These coils 56, 58 inductively couple RF energy into the plasma source region spatially removed from the wafer 30. Thereby, the pedestal biasing is decoupled from the plasma generation.
It has become recognized, particularly in the use of HDP etch reactors, that selectivity in an oxide etch can be achieved by a fluorocarbon etching gas forming a polymer layer upon the non-oxide portions, thereby protecting them from etching, while the oxide portions remain exposed to the etching environment. It is believed that the temperature controlled silicon ring 36 and roof 42 in the reactor of FIG. 2 controls the fluorine content of the polymer, and hence its effectiveness against etching by the fluorocarbon plasma, when the polymer overlies a non-oxide. However, this mechanism seems to be responsible for at least two problems if high selectivity is being sought. If excessive amounts of polymer are deposited on the oxide or nitride surfaces in the contact hole being etched, the hole can close up and the etching is stopped prior to complete etching of the hole. This condition is referred to as etch stop.
Further, the chemistry may be such that the polymer formation depends critically upon the processing conditions. It may be possible to achieve high selectivity with one set of processing conditions, but very small variations in those parameters may be enough to substantially reduce the selectivity on one hand or to produce etch stop on the other. Such variations can occur in at least two ways. The conditions at the middle of the wafer may vary from those at the center. Furthermore, the conditions may change over time on the order of minutes as the chamber warms up or on the order of days as the equipment ages or as chamber parts are replaced. It is felt that hardware can be controlled to no better than .+-.5 or 6%, and a safety margin of 3 to 6 is desired. Mass flow controllers 48 are difficult to control to less than .+-.1 sccm (standard cubic centimeter per minute) of gas flow so gas flows of any constituent gas of only a few sccm are prone to large percentage variations.
These factors indicate that a commercially viable etch process must have a wide process window. That is, large variations in gas composition should produce only minimal changes in the resultant etching.
Several oxide etch processes have been proposed which rely upon higher-order hydrogen-free fluorocarbons and hydrofluorocarbons, both generically referred to as fluorocarbons. Examples of higher-order fluorocarbons are fluoroethane, fluoropropane, and even fluorobutane, both in its linear and cyclic forms. In U.S. Pat. No. 5,423,945, Marks et al. disclose an oxide etch selective to nitride using C.sub.2 F.sub.6 in an HDP etch reactor having a thermally controlled silicon surface. Later process work with the IPS chamber of FIG. 2 has emphasized C.sub.4 F.sub.8 as the principal etchant species. Many of the higher-order fluorocarbons and hydrofluorocarbons are not readily available, especially in semiconductor-grade purity. Furthermore, their toxicity may be unproven, necessitating close review prior to their large-scale use. Even their environmental effects may need further understanding. Hence, it is more desirable to use the already popular fluoromethanes, which include carbon tetrafluoride (CF.sub.4), trifluoromethane (CHF.sub.3), difluoromethane (CH.sub.2 F.sub.2), and monofluoromethane (CH.sub.3 F).